Design of Cmos Low Noise Amplifier using an Automated System-on-Chip Methodology

Abstract

This paper presents an automatic methodology for RF transceiver circuit design. This algorithm is based on analytically driven equations for calculating the required circuit specifications. The presented algorithm is useful for the designers to calculate their initial design parameters closed to the optimum operating point. The analog gm/ID model is used for the circuit design. In order to verify the idea, a CMOS cascade LNA design methodology is presented for a receiver front end. The design methodology is divided into three steps: first the RF amplifier design for the required band; second the band limitation using a tuned circuit. and finally the impedance matching. A MATIAB program is developed for a complete circuit design (MOST’s size, bias current, LS, LD, and LG). The CMOS LNA is simulated at 4 GHz using Cadence CAD tools in the 0.13um CMOS technology parameters. The results are compared to the analytical analysis, and it showed the applicability of the proposed algorithm.