A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology

Abstract

This paper presents a proof-of-concept of the low supply voltage circuit technique for high resolution cyclic analog-to-digital converter (ADC). By utilizing substrate-voltage-control technique for SOTB CMOS, high resolution cyclic ADC can be realized at supply voltage as low as Vdd= 0.8V. A prototype 14bit cyclic ADC is designed and fabricated in 65nm SOTB CMOS technology. Measured DNL=-0.80/1.11LSB, INL=-5.05/3.49LSB are achieved while a 7.81kHz sinusoidal input is sampled at 62.5ksps.