DIFFERENT METHODOLOGIES TO SOLVE VLSI FLOORPLANNING PROBLEM

Abstract

Due to the exponential increase in number of components on a VLSI (Very Large-Scale Integration) chip over the years, there is a need to develop automated algorithms to decide the relative positions of circuits on a chip. In order to improve the performance of a chip, it is essential to deal with multiple objectives including area and wire length during the floor planning phase. Modern very large-scale integration technology is based on fixed-outline floorplan constraints, generally with an objective of minimizing area and wirelength between the modules. This survey paper gives an up-to-date account on various approaches used to solve VLSI floor planning problem. Keywords—Genetic algorithm, Non-slicing floorplan, Soft modules, VLSI floor planning.