A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension

E. Mammei, E. Monaco, A. Mazzanti, F. Svelto
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引用次数: 59

Abstract

Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due to process variations and the stringent reference phase noise to ensure signal integrity calls for an ultra-wide tuning range and low-noise on-chip oscillator. Meeting this target is even more challenging when adopting an ultra-scaled CMOS technology node where key passive components suffer from a reduced quality factor (Q) [1]. In a 32nm node the thickness of metals closer to the substrate is half that in a 65nm process leading, for example, to MOM capacitors with roughly half Q. The penalty is only marginally compensated by the higher transistor ft, improved only by ~20%. Various techniques exploiting alternative tuning implementations have been published recently. Magnetic tuning methods where the equivalent tank inductance is varied through reflection of the secondary coil impedance of a transformer demonstrate outstanding tuning ranges but at the cost of a severe trade-off with tank Q and poor noise FOMs [2,3]. A bank of capacitors switched in and out in an LC tank is the most popular tuning approach [4-6]. However the quality factor is severely degraded, when large ranges are involved. In this work, the switched-capacitor tank of the VCO shown in Fig. 20.3.1 is centered around two different resonance frequencies by splitting the inductor through the switch Msw. In particular, an up-shift is produced when the switch is off due to its parasitic capacitance. The frequency range is significantly increased without compromising tank Q leading to large tuning range and high FOM simultaneously. Prototypes of the VCO have been realized in 32nm CMOS showing the following performances: 31.6% frequency tuning range, minimum phase noise of -118dBc/Hz at 10MHz offset from 40GHz with 9.8mW power dissipation. Despite being realized in an ultra-scaled 32nm standard digital CMOS process without RF thick metal options, the oscillator shows state-of-the-art performances.
33.6 ~ 46.2 ghz 32nm CMOS压控振荡器,最小噪声177.5dBc/Hz,采用电感分裂进行调谐扩展
超宽带宽下的信号处理是毫米波下多gb /s无线收发器设计的关键挑战之一,其中规定了覆盖57GHz至66GHz的信道。进一步考虑由于工艺变化和严格的参考相位噪声引起的扩散,以确保信号完整性,需要超宽调谐范围和低噪声片上振荡器。当采用超大规模CMOS技术节点时,实现这一目标更具挑战性,因为关键无源元件的质量因子(Q)降低了[1]。在32nm节点中,靠近基板的金属厚度是65nm工艺的一半,例如,导致具有大约一半q的MOM电容器,这种损失只能通过更高的晶体管ft来补偿,仅提高了约20%。最近已经发表了各种利用备选调优实现的技术。通过变压器次级线圈阻抗的反射来改变等效槽电感的磁调谐方法显示出出色的调谐范围,但代价是槽Q和差噪声FOMs的严重权衡[2,3]。一组电容器在LC槽中输入和输出是最流行的调谐方法[4-6]。然而,当涉及大范围时,质量因子严重退化。在这项工作中,如图20.3.1所示的VCO的开关电容槽通过开关Msw将电感分开,以两个不同的谐振频率为中心。特别是,当开关由于其寄生电容而关闭时,会产生上移。频率范围显著增加而不影响坦克Q导致大的调谐范围和高FOM同时。该压控振荡器的原型已在32nm CMOS上实现,具有以下性能:31.6%的频率调谐范围,在40GHz的10MHz偏移时最小相位噪声为-118dBc/Hz,功耗为9.8mW。尽管该振荡器采用了超大尺寸的32纳米标准数字CMOS工艺,没有射频厚金属选项,但仍具有最先进的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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