Investigation of p-GaN Gate HEMT using Removal Si Substrate and part of Buffer Layer

IF 1.3 Q3 COMPUTER SCIENCE, INFORMATION SYSTEMS

IET Networks Pub Date : 2022-10-14 DOI:10.1109/IET-ICETA56553.2022.9971618

Y. Lin, Y. Chiu, E. Chang

引用次数: 0

Abstract

Normally-off p-GaN gate high electron mobility transistor (HEMT) on Si substrate using the back-side via process was investigated. We removed the Si substrate and part of the GaN carbon-doped layer. A 100 nm thickness of SiO2 layer is deposited on the back-side via to obstruct the buffer leakage, and a 1um thick gold is electroplated to improve the self-heating effect. With and without the backside via process, the threshold voltages are 0.92 and 1.45 V, the on/off drain current ratios are 5×1010 and 5×108, the subthreshold swings are 154 and 224 mV/dec, the static on-resistances are 24.77 and 27.55 Ω.mm, and the dynamic on-resistance ratios are 1.18 and 1.3.

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去除硅衬底和部分缓冲层制备p-GaN栅极HEMT的研究

研究了硅衬底上常关p-GaN栅极高电子迁移率晶体管(HEMT)。我们去除了Si衬底和部分GaN碳掺杂层。在背面孔道上沉积100 nm厚度的SiO2层以阻断缓冲泄漏，并电镀1um厚的金以提高自热效果。有无后通孔工艺，阈值电压分别为0.92和1.45 V，漏极通断电流比分别为5×1010和5×108，亚阈值振荡分别为154和224 mV/dec，静态导通电阻分别为24.77和27.55 Ω。Mm，动态通阻比分别为1.18和1.3。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Networks COMPUTER SCIENCE, INFORMATION SYSTEMS-

CiteScore

5.00

自引率

0.00%

发文量

审稿时长

33 weeks

期刊介绍： IET Networks covers the fundamental developments and advancing methodologies to achieve higher performance, optimized and dependable future networks. IET Networks is particularly interested in new ideas and superior solutions to the known and arising technological development bottlenecks at all levels of networking such as topologies, protocols, routing, relaying and resource-allocation for more efficient and more reliable provision of network services. Topics include, but are not limited to: Network Architecture, Design and Planning, Network Protocol, Software, Analysis, Simulation and Experiment, Network Technologies, Applications and Services, Network Security, Operation and Management.