{"title":"BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs","authors":"P. Su, S. Fung, S. Tang, F. Assaderaghi, C. Hu","doi":"10.1109/CICC.2000.852647","DOIUrl":null,"url":null,"abstract":"BSIMPD, a physics-based SPICE model, is developed for bridging deep-submicron CMOS designs using partially-depleted SOI technologies. Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for a sound base of scalability and robustness, BSIMPD captures SOI-specific dynamic behaviors with its built-in floating-body, self-heating and body-contact models. A parameter-extraction strategy is demonstrated, and the simulation efficiency is studied. The model has been tested extensively within IBM on state-of-the-art high speed SOI technologies. It has been implemented in many circuit simulators.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"13 1","pages":"197-200"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 32
Abstract
BSIMPD, a physics-based SPICE model, is developed for bridging deep-submicron CMOS designs using partially-depleted SOI technologies. Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for a sound base of scalability and robustness, BSIMPD captures SOI-specific dynamic behaviors with its built-in floating-body, self-heating and body-contact models. A parameter-extraction strategy is demonstrated, and the simulation efficiency is studied. The model has been tested extensively within IBM on state-of-the-art high speed SOI technologies. It has been implemented in many circuit simulators.