Exploration of Heterogeneous FPGA Architectures

IF 3 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Umer Farooq, H. Parvez, H. Mehrez, Z. Marrakchi
{"title":"Exploration of Heterogeneous FPGA Architectures","authors":"Umer Farooq, H. Parvez, H. Mehrez, Z. Marrakchi","doi":"10.1155/2011/121404","DOIUrl":null,"url":null,"abstract":"Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hardblocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.","PeriodicalId":43583,"journal":{"name":"International Journal of Reconfigurable Computing","volume":"19 1","pages":"37-44"},"PeriodicalIF":3.0000,"publicationDate":"2010-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Reconfigurable Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1155/2011/121404","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 26

Abstract

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hardblocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.
异构FPGA架构的探索
基于网格的异构fpga由于其面积、速度和功率优于同类fpga,在工业和学术界中广泛使用。这些fpga包含逻辑块和硬块的混合物,其中硬块排列在固定列中,因为它们提供了一个简单而紧凑的布局。但是,将硬块放置在固定列中可能会导致逻辑和路由资源的利用不足,并且随着硬块类型的增加,这个问题会进一步恶化。这项工作探索并比较了基于网格的FPGA的不同地板规划技术,以确定它们对架构的面积、性能和功耗的影响。提出了一种基于树的体系结构;与基于网格的体系结构不同,异构树的分层规划不影响其路由需求。在三组基准电路中对网格和树结构进行了评估。实验结果表明,基于网格的FPGA地板规划比基于列的地板规划更灵活,可以获得更好的效果。结果表明,与网格FPGA的不同布局相比,树型结构具有更好的面积、性能和功耗。
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来源期刊
International Journal of Reconfigurable Computing
International Journal of Reconfigurable Computing COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
1.50
自引率
0.00%
发文量
2
审稿时长
33 weeks
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