A new Gated -ground- sleep architecture for ultra low leakage of SRAM cell

Abstract

As down-scaling of transistors and up-scaling of technology creating an overwhelming inversely proportional scenario in today's VLSI era, three major components taking into account while designing of CMOS memory cells. As the technology shrinks down, the power dissipation widely impacts to SRAM cells. Along with the power consumption, delay and stability of SRAM cell is also becoming a challenging issue day by day. In this paper, a low power designing approach is being introduced taking advantages of combination architectures of Transmission Gate logic and Gated ground sleep logic. The Transmission Gate invokes a leakage free sub-threshold scenario when Gated ground sleep logic provides a swiftly stacking effect which jointly can induce lowering down power consumption in SRAM cell. This new approach can significantly reduce power consumption upto 75% compared to conventional 6T-SRAM cell. All the experimental works are done by tSPICE 16 with 0.25μm technology.