An efficient turbo decoder architecture for IMT2000

Abstract

In this paper, we present an efficient architecture of turbo decoder for IMT2000 system. We introduce a base 2 logarithmic maximum a-posteriori algorithm (log/sub 2/MAP) whose architecture is simpler than that of the conventional natural logarithmic MAP algorithm (log/sub e/MAP). With log/sub 2/MAP, we obtain a '2 function' which is simpler than the 'E function' used by log/sub e/MAP. In order to implement the architecture of the 2 function, we use approximated binary logarithmic algorithm (ABLA) which has been usefully adopted in DSP. Using ABLA, we can reduce the RAM size from 1 kbytes to 96 bytes, which can be implemented using combinational logic gates. Also, we design the simple normalization module by making all the branch metrics to have positive values. We introduce reverse interleaver and deinterleaver to calculate forward and reverse state metric simultaneously. Using our architecture, we obtained BER of 9.79/spl times/10/sup -7/ at Eb/No of 2 dB and 5th iterations for constraint length K=4, code rate R=1/2, jumping window of 512 bits and interleaver size of 1144 bits, i.e. data rate of 57.6 kbps.