Design of low power and area efficient half adder using pass transistor and comparison of various performance parameters

Abstract

The main objective of this paper is to design the low power consumption and less area occupied combinational circuit here we designed half adder circuit using three different logic styles: CMOS NAND gate logic, CMOS transmission gate logic, and NMOS pass transistor logic. All the circuits are simulated and compared by using Cadence Virtuoso IC 6.1.5, 180nm CMOS Technology with the supply voltage of 5 V. In this paper we compare different performance parameters of these three logic styles, like power consumption, Number of transistors, propagation delay, rise time, fall time etc.