NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

T. Miwa, Junichi Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio
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引用次数: 59

Abstract

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.
NV-SRAM:一种具有备用铁电电容器的非易失性SRAM
本文展示了新的电路技术,使0.25-/spl mu/m的ASIC SRAM宏成为非易失性的,只有17%的单元面积开销(NV-SRAM:非易失性SRAM)。新的金属电容/过孔堆叠式插塞工艺技术使得NV-SRAM单元由一个六晶体管ASIC SRAM单元和两个堆叠在SRAM部分上的备用铁电电容器组成成为可能。Vdd/2板线架构使读/写疲劳几乎可以忽略不计。成功地制作了一个512字节的测试芯片,显示了与ASIC技术的兼容性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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