T. Miwa, Junichi Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio
{"title":"NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors","authors":"T. Miwa, Junichi Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio","doi":"10.1109/CICC.2000.852619","DOIUrl":null,"url":null,"abstract":"This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"59","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 59
Abstract
This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.