Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process

Abstract

We have investigated the degradation of thick gate oxide in the conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide operating under the bias of 1.8 and 2.5 V, respectively, on a single chip, a novel dual gate oxide process flow, without gate oxide thinning at STI corner, is presented. Our new integration of dual gate oxide shows an improved gate oxide reliability compared to the conventional process.