{"title":"High-Speed Integrated Monolithic Thin-Film Compatible Diode Transistor Logic Circuits","authors":"N. Fuschillo, J. Kroboth, T. Pardue","doi":"10.1109/TA.1965.4319843","DOIUrl":null,"url":null,"abstract":"A group of high-speed, low-power monolithic thin-film diode transistor logic (DTL) circuits is described for computer and counter applications. A basic die rather than a master wafer approach was taken since most circuits in the DTL system can be fabricated in terms of the basic single-NAND gate. Propagation delay times of 4.5 nanoseconds for the basic NAND gate have been achieved, with a typical average of 6 nanoseconds at a power level of 11.7 mw. Average set and reset times on RS flip-flops are typically 16 and 18 nanoseconds, respectively. The basic die pattern is such that a fan-in expander, single-NAND gate, dual-NAND gate, RS flip-flop, and a binary element can be made in single-chip form by simple changes in the final interconnection mask. Methods of measurement and applications to counters, adders, and shift registers are discussed.","PeriodicalId":13050,"journal":{"name":"IEEE Transactions on Aerospace","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1965-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Aerospace","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TA.1965.4319843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A group of high-speed, low-power monolithic thin-film diode transistor logic (DTL) circuits is described for computer and counter applications. A basic die rather than a master wafer approach was taken since most circuits in the DTL system can be fabricated in terms of the basic single-NAND gate. Propagation delay times of 4.5 nanoseconds for the basic NAND gate have been achieved, with a typical average of 6 nanoseconds at a power level of 11.7 mw. Average set and reset times on RS flip-flops are typically 16 and 18 nanoseconds, respectively. The basic die pattern is such that a fan-in expander, single-NAND gate, dual-NAND gate, RS flip-flop, and a binary element can be made in single-chip form by simple changes in the final interconnection mask. Methods of measurement and applications to counters, adders, and shift registers are discussed.