Mathematical Model of Transposition Chaotic Encryption System Based on Field-Programmable Gate Arrays for Multimedia Data

Abstract

In the paper, the mathematical model of memory consumption and through-put parameter estimation of a cryptographic system that employs transposition chaotic maps is investigated. The target platform for the system implementation is Field-Programmable Gate Array (FPGA) devices. The proposed mathematical model takes into account limitations of FPGA circuits and can be used to assess usage of FPGA memory resources preliminary and to evaluate throughput efficiency of the encryption system. First, expressions for memory consumption are introduced. The second part is devoted to analysis of the system throughput. Different architectures for memory organization have been considered in the paper as well as all stages of the cipher pipeline. The architectures are characterized by the different level of parallelism on the level of message processing that results in variations in throughput value. The work presents generalized expression for throughput estimation for all the considered cipher architectures. It allows the designer of the system to select an FPGA die that fulfills the basic requirements for cryptographic system implementation.