Power efficient architecture for (3,6)-regular low-density parity-check code decoder

Abstract

Most of the current LDPC decoder VLSI architecture research focuses on increasing system throughput or reducing hardware implementation complexity, but neglects power consumption. In this paper, we analyze the power consumption of the (3,k)-regular LDPC decoder architecture. Our analysis shows that 95% of the power consumption is consumed in accessing the memory. A new architecture is proposed which reduces memory access, hence power consumption, without sacrificing the performance. Experimental results show reduction in the power consumption by 14% and lower hardware complexity without sacrificing the Bit-Error-Ratio performance compared to previous work.