V. Catania, Andrea Mineo, Salvatore Monteleone, Davide Patti
{"title":"A Low-resource and Scalable Strategy for Segment Partitioning of Many-core Nano Networks","authors":"V. Catania, Andrea Mineo, Salvatore Monteleone, Davide Patti","doi":"10.1145/2613908.2613915","DOIUrl":null,"url":null,"abstract":"In this work we introduce the design and implementation of DiSR, a distributed approach to topology discovery and defect mapping in nanoscale network-on-chip scenario. We first describe the conceptual elements and the execution model of DiSR, showing how the open-source Nanoxim platform has been used to evaluate the proposed approach in terms of node coverage and scalability achieved when establishing a segment partitioning. Next, in order to demostrate the feasibility of the proposed strategy in the context of the limited node resources, we propose both a schematic and gate-level hardware implementation of the required control logic and storage. Results show a relatively acceptable impact, ranging from 10 to about 20% of the 10,0000 transistors budget available for each node.","PeriodicalId":84860,"journal":{"name":"Histoire & mesure","volume":"31 1","pages":"17-24"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Histoire & mesure","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2613908.2613915","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this work we introduce the design and implementation of DiSR, a distributed approach to topology discovery and defect mapping in nanoscale network-on-chip scenario. We first describe the conceptual elements and the execution model of DiSR, showing how the open-source Nanoxim platform has been used to evaluate the proposed approach in terms of node coverage and scalability achieved when establishing a segment partitioning. Next, in order to demostrate the feasibility of the proposed strategy in the context of the limited node resources, we propose both a schematic and gate-level hardware implementation of the required control logic and storage. Results show a relatively acceptable impact, ranging from 10 to about 20% of the 10,0000 transistors budget available for each node.