Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget

Abstract

This paper presents a novel exploration process of an optimal fault tolerant data path based on user specified power and delay budget during high level synthesis (HLS) that is capable of masking error occurred through single and multi cycle transient faults. The exploration framework is driven through bio-mimicking of E. Coli bacterium lifecycle. The major novelties of this approach are as follows: a) novel multi-cycle fault tolerant algorithm, b) novel design space exploration (DSE) approach that combines proposed fault tolerant algorithm along with user specified conflicting power-delay constraint that guides this intractable search problem to reach an optimal solution, c) novel double modular redundant (DMR) system with equivalent circuit scheme that performs the equivalent function of extracting the correct output as conventionally done using the concept of triple modular redundant (TMR) and voter. Results indicated an average improvement in quality of results (QoR) of >24% and reduction in hardware usage of > 57 % were obtained compared to a recent similar approach.