A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Abstract

Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.