Challenges and best practices in advanced silicon debug

Abstract

Which is better for the debug of root causes for post-silicon issues with functionality, performance, or power: functional test on ATE, system-level test, or structural test? The panel will discuss pros and cons of the different approaches. Functional or system tests have traditionally been used for debugging functionality, performance and power related issues for high performance microprocessors or complex Systems-on-Chip. The functional approach can be expensive in infrastructure investment and in resources. Much of the infrastructure may not be usable from product to product. Results may not provide all the information for an effective post-silicon design optimization strategy. Structural tests such as scan or different forms of BIST can provide greater coverage, but does not know if a design is correct. Scan-based tests can be used for performance debug and is easier to automate. Scan takes advantage of existing architectures in a design and the automated test pattern generation process. Due to the limited number of at-speed capture cycles, scan tests can be easier to debug as more information of the chip behavior at the point of failure is available. However, scan can also test non-functional paths or easily generate over-kill or over stress conditions. How can scan be used if it can cause a false performance issue? Diagnosing power related issues can be a complex problem. Besides characterizing the power consumption during system testing, parametric tests and test-structure assisted test-based learning often could provide a quick read into potential power issues. The panel will analyze pro's and con's of various types and combinations of advance silicon debug to highlight the challenges and best practices available. Panelists represent years of experience in Silicon debug in Chip, Board, and System test and debug as well as EDA.