RF voltage limiters for passive differential UHF RFID front-ends in a 40 nm CMOS technology

Abstract

Passive differential UHF radiofrequency identification (RFID) front-ends may experience at high input power levels voltage amplitudes exceeding the maximum voltage ratings of the respective CMOS technology. The risk of damaging overvoltage stress increases significantly with circuits moving to technologies below the 100nm node. This work gives a discussion on characteristics of central building blocks of a UHF RFID frontend in a 40nm low-power CMOS technology under high-power conditions. The investigation reveals the limitations of front-ends without dedicated RF limiter structures. Thus, we present two stand-alone RF voltage limiter designs that mitigate overvoltage stress risks. Simulation results demonstrate the capability of the two RF limiter circuits to restrict the voltage amplitude to values of lower than 1.1V at an available power of 20 dBm.