A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-24 DOI:10.1109/CICC.2000.852676

G. Bollati, A. Dati, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli, P. Gadducci, Stefano Marchese, D. Ottini, Valerio Pisati, F. Rezzi, A. Rossi, P. Savo, C. Tonci, R. Castello

引用次数: 1

Abstract

A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.

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具有奇偶校验和16状态时变Viterbi的450mbit /s并行读写通道

介绍了一种工作速度高达450mbit /s的PRML读写集成电路。该芯片实现了一个16态EPR4奇偶校验时变Viterbi检波器和一个数字伺服。带有奇偶校验的24/26码提高了对白噪声、媒体噪声和偏离轨道条件的鲁棒性。该器件集成在成熟的0.35 /spl mu/m BiCMOS技术中，芯片尺寸为13 mm/sup 2/(步进和重复)，在450mbit /s下功耗为1.9 W(读模式下)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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