Continuous real-world inputs can open up alternative accelerator designs

B. Belhadj, A. Joubert, Zheng Li, R. Héliot, O. Temam
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引用次数: 72

Abstract

Motivated by energy constraints, future heterogeneous multi-cores may contain a variety of accelerators, each targeting a subset of the application spectrum. Beyond energy, the growing number of faults steers accelerator research towards fault-tolerant accelerators. In this article, we investigate a fault-tolerant and energy-efficient accelerator for signal processing applications. We depart from traditional designs by introducing an accelerator which relies on unary coding, a concept which is well adapted to the continuous real-world inputs of signal processing applications. Unary coding enables a number of atypical micro-architecture choices which bring down area cost and energy; moreover, unary coding provides graceful output degradation as the amount of transient faults increases. We introduce a configurable hybrid digital/analog micro-architecture capable of implementing a broad set of signal processing applications based on these concepts, together with a back-end optimizer which takes advantage of the special nature of these applications. For a set of five signal applications, we explore the different design tradeoffs and obtain an accelerator with an area cost of 1.63mm2. On average, this accelerator requires only 2.3% of the energy of an Atom-like core to implement similar tasks. We then evaluate the accelerator resilience to transient faults, and its ability to trade accuracy for energy savings.
持续的现实世界输入可以打开可选择的加速器设计
受能量限制的影响,未来的异构多核可能包含各种各样的加速器,每个加速器针对应用范围的一个子集。除了能量之外,越来越多的故障将加速器研究转向容错加速器。在本文中,我们研究了一种用于信号处理应用的容错和节能加速器。我们通过引入一种依赖于一元编码的加速器来改变传统的设计,这一概念很好地适应了信号处理应用的连续输入。一元编码使许多非典型的微架构选择能够降低面积成本和能源;此外,一元编码在瞬态故障数量增加时提供了优雅的输出退化。我们介绍了一种可配置的混合数字/模拟微架构,能够实现基于这些概念的广泛的信号处理应用,以及利用这些应用的特殊性的后端优化器。对于一组五种信号应用,我们探索了不同的设计权衡,并获得了面积成本为1.63mm2的加速器。平均而言,这个加速器只需要一个类似原子核心的2.3%的能量就能完成类似的任务。然后,我们评估了加速器对瞬态故障的恢复能力,以及它以准确性换取节能的能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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