Design, manufacture and test-quality cost estimation

J. M. Gilbert, I. Bell, D. R. Johnson
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引用次数: 5

Abstract

This paper describes the adaptation of the conformability analysis technique to the assessment of functional, manufacturing and test capability of PCB level electronic circuits. It combines process capability indices and failure modes and effects analysis (FMEA) with cost mapping to allow the quality costs associated with design and manufacture induced faults to be estimated and the effectiveness of test strategies in reducing these costs to be determined. It allows the trade-off between these costs and the component, manufacturing process and test costs to be explored. The technique is particularly applicable to the relatively low complexity analogue and mixed signal safety critical circuits typically found in automotive and aircraft electronic systems.
设计,制造和测试质量成本估算
本文介绍了一致性分析技术在PCB级电子电路功能、制造和测试能力评估中的应用。它将过程能力指数、失效模式和影响分析(FMEA)与成本映射相结合,从而可以估计与设计和制造引起的故障相关的质量成本,并确定降低这些成本的测试策略的有效性。它允许在这些成本与组件、制造过程和测试成本之间进行权衡。该技术特别适用于汽车和飞机电子系统中相对低复杂度的模拟和混合信号安全关键电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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