Manufacturability Aware Routing in Nanometer VLSI

Q1 Computer Science

Foundations and Trends in Electronic Design Automation Pub Date : 2010-04-15 DOI:10.1561/1000000015

D. Pan, Minsik Cho, Kun Yuan

引用次数: 16

Abstract

1: Introduction 2: CMP Aware Routing 3: Random-Defect Aware Routing 4: Lithography Aware Routing 5: Redundant Via Aware Routing 6: Antenna-Effect Aware Routing 7: Other DFM Issues in VLSI Routing 8: Conclusions. References

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纳米VLSI中可制造性感知路由

1:介绍2:CMP感知路由3:随机缺陷感知路由4:光刻感知路由5:冗余Via感知路由6:天线效应感知路由7:VLSI路由中的其他DFM问题8:结论。参考文献

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Foundations and Trends in Electronic Design Automation ENGINEERING, ELECTRICAL & ELECTRONIC-

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期刊介绍： Foundations and Trends® in Electronic Design Automation publishes survey and tutorial articles in the following topics: - System Level Design - Behavioral Synthesis - Logic Design - Verification - Test - Physical Design - Circuit Level Design - Reconfigurable Systems - Analog Design Each issue of Foundations and Trends® in Electronic Design Automation comprises a 50-100 page monograph written by research leaders in the field.