Li Miao, Yang Xiaohui, D. Zibin, Chen Tao, He Liangsheng
{"title":"Research and implementation of micro-architecture for Elliptic Curve Cryptography processor","authors":"Li Miao, Yang Xiaohui, D. Zibin, Chen Tao, He Liangsheng","doi":"10.1109/EDSSC.2011.6117653","DOIUrl":null,"url":null,"abstract":"With the characteristics of computing compression, Elliptic Curve Cryptography (ECC) can be exploited parallel processing function by adopting VLIW architecture. Based on VLIW, the micro-architecture composition, pipeline structure and clustered architecture of ECC processor have been researched, and a microarchitecture design method for ECC processor has been presented. Using FPGA and under 0.18µm CMOS technology, a prototype has also been implemented. The results prove that the proposed micro-architecture for ECC processor can not only guarantee high flexibility for arbitrary ECC algorithms, but also achieve high performance.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
With the characteristics of computing compression, Elliptic Curve Cryptography (ECC) can be exploited parallel processing function by adopting VLIW architecture. Based on VLIW, the micro-architecture composition, pipeline structure and clustered architecture of ECC processor have been researched, and a microarchitecture design method for ECC processor has been presented. Using FPGA and under 0.18µm CMOS technology, a prototype has also been implemented. The results prove that the proposed micro-architecture for ECC processor can not only guarantee high flexibility for arbitrary ECC algorithms, but also achieve high performance.