Design of Efficient Cyclic Redundancy Check-32 using FPGA

Abstract

In Data Integrity, Cyclic Redundancy Check (CRC) is error detection technique. CRC treat a group of binary bits of a message by dividing it by a fixed binary number, the resulted remainder is the checksum that will be attached to the message. On the receiver side the same division could be performed and the receiver can compare the remainder with the transmitted checksum. This paper explains the design of CRC32 that used in Ethernet using Field Programmable Gate Array (FPGA) Virtex-7. The design built based on lookup tables and slicing-by-16 algorithm that performed the calculations of the CRC32 in parallel. Xilinx ISE used as IDE and I-Sim used for the simulation. The resulted processing time is equal to 1.250 ns with low power consumption and low device utilization.