Combinational and sequential standard cell design using Radiation Hardened By Design (RHBD) Technique

Abstract

The work in this paper centres around comparison amongst conventional and RHBD technique based combinational and sequential standard cells in 0.18μmCMOS technology using SCL PDK in Cadence Virtuoso. In space radioactive particles (proton, neutrons, $\alpha$) and heavy ions makes the biggest threat to Integrated Circuits (IC). With continuously decreasing feature size and lowering of the supply voltage, causes Single Event Transients (SETs) which is becoming a major problem for both combinational and sequential digital circuits in the Deep Submicron technology (DSM). The proposed C- element based cells investigated are Inverter, NAND gate, Buffer and D-Flip Flop. Schematic and layout of these cells are developed using Cadence Virtuoso tool. Circuits which are designed with the RHBD approaches are more tolerant to Single Event Effects (SEE), have better noise immunity and less static power consumption. The reduction in the average power in proposed style is 94% and the delay reduction is 85% as compared to DCVSL methodology.