Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical PRNG on FPGA

Abstract

In this study, successful real-time implementation of discrete-time chaotic zigzag map as a Random Number Generator on field-programmable gate array (FPGA) environment is presented. For hardware implementation, in addition to ready-use circuit elements defined on 32-bit floating-point numbers, very high-speed integrated circuit hardware description language (VHDL) is used. In the scope of this study, cryptographic critical competencies such as system reliability and randomness quality related to nonlinear dynamic behaviour of zigzag map are examined. H function post - processing technique is used in the system for random numbers with low statistical quality achieved from chaotic system. Also NIST 800-22 standard test technique is used for statistical verification of bit sequences obtained from the generator. In addition to its practical applicability, the results show that the zigzag map can be used as a random number generator for embeded cryptographic applications.