Design, test & repair methodology for FinFET-based memories

Abstract

Due to their spatial structures, FinFETs have several advantages including controlled Fin body thickness, low threshold voltage variation, reduced variability and lower operating voltage. Because of the special structures of FinFET transistors, modern FinFET-based memories can lead to defects that require new test and repair solutions. Usually the existing approaches are not able to provide appropriate level of defect coverage and yield for FinFET memories. This presentation will discuss the design complexity, defect coverage and yield challenges of FinFET-based memories and introduce new methods to address them. This will include new design techniques, new FinFET specific defect and their coverage, as well as yield optimization infrastructure. Based on the obtained results, the presentation will also cover the synthesis of test algorithms for detection of diagnosis of FinFET memories s and built-in self-test infrastructure with a high efficiency of test and repair capability to ensure adequate yield improvement for FinFET-based memories. The presented methodology is validated by silicon data from multiple FinFET-based embedded memory technologies.