Experimental investigation of RSFQ circular shift registers

Abstract

Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.