A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS

Abstract

A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (~9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300μA over the whole input range.