A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

Abstract

Demands for battery-powered consumer electronics have driven the evolution of power-efficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery life and shrinking form-factors. Flicker noise poses an issue for such systems although the use of well-known techniques in state-of-the-art designs such as chopper stabilization [1]–[2] are often sufficient for its mitigation. Alternatively, the pseudo-pseudo-differential (PPD) architecture [3] has demonstrated flicker cancellation through the use of single-ended circuits although area and power savings promised by this technique remain undemonstrated. This paper presents a DT single-loop DSM audio ADC utilizing a single-ended ring-amplifier-based integrator to achieve 108.8dB DR with 203.5µW power consumption within a compact area of 0.0375mm2. The use of the PPD architecture with a merged adder contribute to this work's state-of-the-art power and area efficiency.