Design, technology and yield in the post-moore era

Abstract

Looking forward along the technology roadmap, we see a complex, shifting landscape in which to attempt to ramp yield. Optical lithography is not providing any direct scaling benefit, and the available workarounds such as multiple patterning and mix-and-match lithography techniques greatly complicate design-technology co-optimization (DTCO) and yield/cost understanding. The silicon FinFET will give way to nanowires and/or new channel materials, and eventually force the examination of entirely new transistor topologies. Interconnect R's and C's will upset the FET/wire balance and with it some of our accumulated design/yield understanding, and reliability will play an increasing role in the determination of final cost. This talk will examine these technology roadmap topics with a view toward technology bring-up.