Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS

Abstract

Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1–3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write access. This paper presents two STT-MRAM access schemes: a negative-resistance read scheme (NRRS) that guarantees non-destructive read by design, and a negative-resistance write scheme (NRWS) that, on average, reduces the write power consumption by 10.5%. A fabricated and measured test-chip in 0.13µm CMOS confirms both properties.