Scan chain design for three-dimensional integrated circuits (3D ICs)

Xiaoxia Wu, P. Falkenstern, Yuan Xie
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引用次数: 67

Abstract

Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed to facilitate DFT (Design-For-Test). Recently, three-dimensional (3D) technologies have been proposed as a promising solution to continue technology scaling. In this paper, we study the scan chain construction for 3D ICs, examining the impact of 3D technologies on scan chain ordering. Three different 3D scan chain design approaches (namely, VIA3D, MAP3D, and OPT3D) are proposed and compared, with the experimental results for ISCAS89 benchmark circuits. The advantages as well as disadvantages for each approach are discussed. The results show that both MAP3D and VIA3D approaches require no changes of 2D scan chain algorithms, but OPT3D can achieve the best wire length reduction for the scan chain design. The average scan chain wire length of six ISCAS89 benchmarks obtained from OPT3D has 46.0% reduction compared to the 2D scan chain design. To the best of our knowledge, this is the first study on scan chain design for 3D integrated circuits.
三维集成电路(3D ic)扫描链设计
扫描链被广泛用于提高集成电路设计的可测试性。在传统的二维集成电路设计中,已经提出了各种关于扫描链构造的设计技术来促进DFT (design - for - test)。最近,三维(3D)技术被提出作为一种有前途的解决方案来继续技术扩展。本文研究了三维集成电路的扫描链结构,考察了三维技术对扫描链排序的影响。提出了三种不同的三维扫描链设计方法(即VIA3D、MAP3D和OPT3D),并与ISCAS89基准电路的实验结果进行了比较。讨论了每种方法的优点和缺点。结果表明,MAP3D和VIA3D方法都不需要改变二维扫描链算法,但OPT3D可以实现扫描链设计的最佳线长缩减。从OPT3D获得的六个ISCAS89基准测试的平均扫描链线长度与2D扫描链设计相比减少了46.0%。据我们所知,这是第一个三维集成电路扫描链设计的研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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