{"title":"Wideband CDMA receiver for WLL system","authors":"Y. Jeong, J.S. Kim, Y.G. Bahg","doi":"10.1109/ICICS.1997.647161","DOIUrl":null,"url":null,"abstract":"WLL is an access system that uses a wireless link to connect subscribers to their local exchange in place of conventional copper cable. We propose a common air interface for the wideband CDMA WLL system. This paper describes the design and implementation of a digital receiver ASIC for the proposed wideband CDMA WLL system. The proposed reverse link transmitter structure is described. Then the design specification of the reverse link receiver is described. Operation of the implemented reverse link receiver ASIC is verified by system timing simulation. The total gate number of the code acquisition module, code tracking and data demodulation module, and Viterbi decoder module is about 150,000. For the purpose of ASIC implementation, 0.6 /spl mu/m CMOS technology is used. The implemented reverse link receiver ASIC can operate at clock frequencies up to 65.536 MHz.","PeriodicalId":71361,"journal":{"name":"信息通信技术","volume":"47 1","pages":"560-563 vol.1"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"信息通信技术","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ICICS.1997.647161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
WLL is an access system that uses a wireless link to connect subscribers to their local exchange in place of conventional copper cable. We propose a common air interface for the wideband CDMA WLL system. This paper describes the design and implementation of a digital receiver ASIC for the proposed wideband CDMA WLL system. The proposed reverse link transmitter structure is described. Then the design specification of the reverse link receiver is described. Operation of the implemented reverse link receiver ASIC is verified by system timing simulation. The total gate number of the code acquisition module, code tracking and data demodulation module, and Viterbi decoder module is about 150,000. For the purpose of ASIC implementation, 0.6 /spl mu/m CMOS technology is used. The implemented reverse link receiver ASIC can operate at clock frequencies up to 65.536 MHz.