Performance analysis of process bus communication in a Central Synchrocheck application

Abstract

The process bus communication in substations facilitates the exchange of data from multiple bays to different bay level and station level devices. This enables the realization of applications that depend on data from multiple bays, e.g. Central Synchrocheck. Such applications have high availability and hard real-time requirements. In this paper, different process bus topology variants using the Parallel Redundancy Protocol (PRP) and High-availability Seamless Ring (HSR) for Central Synchrocheck application are investigated. The performance of these topology variants is analyzed under worst-case communication loads for different sizes of substations. To this end, simulation models for Merging Units, Central Synchrocheck device, PRP and HSR network elements are developed in OMNEST. These models are used to build different network topologies. The network topologies are simulated to gather the end-to-end latency statistics for GOOSE and SV messages. The simulation analysis distinguishes the topology variants that offer better performance for a certain substation size and also indicates for which process bus network segments Gigabit Ethernet is appropriate.