Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510576

Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama

引用次数: 1

Abstract

A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.

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并行图像处理RAM的控制与同步方案，具有128个处理器单元和16mb DRAM

新开发的并行图像处理RAM (PIP-RAM)在单个芯片上集成了128个处理器元件和16 mb DRAM。本文提出了三种新颖的电路设计技术:处理器和存储器之间的数据路径控制和同步方案;一种使刷新操作与算术逻辑操作并行的刷新方案;以及一种特殊的块冗余方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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