A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS

Abstract

We present a power- and area-efficient 24GS/s, 6b, 16-way time-interleaved (TI) ADC array, featuring a voltage-time (v/t) hybrid two-step structure for high-speed and low-power operation, a crosstalk-free SAR DAC topology and a non-hierarchical sampling frontend obviating reference and input buffers, respectively, for power and area savings. Background timing-skew calibration via dithering a reference ADC is also reported. Fabricated in 28nm CMOS, the prototype ADC array consumes 23mW at 24GS/s and measures an SNDR/SFDR of 35/54dB for a low-frequency input and 29/41dB for a Nyquist input, respectively. The core area of the ADC is 0.03mm2.