A 0.5-V multi-channel low-noise readout front-end for portable EEG acquisition.

Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference Pub Date : 2015-01-01 DOI:10.1109/EMBC.2015.7318492

Wen-Yen Huang, Yu-Wei Cheng, Kea-Tiong Tang

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引用次数: 0

Abstract

This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small Gm-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply.

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一种用于便携式脑电图采集的0.5 v多通道低噪声读出前端。

本文提出了一种适用于脑电图采集的低噪声读出前端。该芯片包括8通道全差分仪表放大器，利用斩波稳定技术来降低闪烁噪声，每个放大器都带有一个小型Gm-C低通滤波器，一个可编程增益放大器，以及一个带有DAC切换检测逻辑的10位连续逼近寄存器(SAR) ADC。该芯片采用台积电90nm CMOS工艺制造。低噪声读出前端的模拟频响范围为0.57 Hz ~ 213 Hz，可编程增益范围为54.4 dB ~ 87.6 dB，脑电带宽内的综合输入参考噪声为0.358 μVrms，噪声效率因子(NEF)为2.43，功率效率因子(PEF)为2.95。在0.5 v电源下，整个系统功耗为32.08 μW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference

CiteScore

2.20

自引率

0.00%

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