Performance Evaluation Based on Placement Planning of Logic Blocks in FPGA Design

Abstract

The Field Programmable Gate Arrays (FPGAs) show reasonable improvements in the speed and power constraints which makes a platform for the digital circuits implementations. For designing an FPGA, synthesis tools are used which performs various minimizations and optimizations techniques. The synthesis tools use the RTL representation of the design with a set of timing constraints and generate the corresponding gate-level netlists. Today, the most advanced Xilinx Vivado Design Suite is used for the FPGA design as a synthesis tool. In some cases, the Xilinx Vivado can’t meet the designer’s required delay and power constraints. So the main aim of this project is to evaluate the improvements in performance by planning the placements of the logic blocks to meet the required speed and power constraints of the designer in Xilinx Vivado software.