FPGA implementation of high performance Fast Page Mode dynamic random access memory

Abstract

A digital system frequently requires memory for storage. To facilitate this requirement, FPGAs offer different types of memory, ranging from block RAM, a highly distributed RAM in the form of the multiple LUTs, right down to the storage of data in the flip-flops. However, unlike the conventional RAMs, dynamic random access memory (DRAM) is best suited for larger volumes of memory, because it permits complex yet advanced levels of integration, occupies less space in motherboard due to reduced feature size, and more importantly, it is inexpensive. Dynamic RAMs evolved from the earliest 1- kilobit (KB) generation to the modern 1-gigabit (GB) generation through the advances and developments in not only semiconductor process but also circuit design technology. This paper proposes resistor transistor logic (RTL) design of the firstgeneration and second-generation high performance (Fast Page Mode) dynamic random access memory. The simulation diagram was experimented using the Verilogger Test bench pro 6.5 software. The timing as well as device utilization summary has been presented in this paper and compared for both normal and fast page mode DRAM. For fast page mode DRAM, the combinational path delay was less compared to the first generation DRAM.