Design Flow for The Implementation of Obfuscated Finite State Machines

IF 1.3 Q3 COMPUTER SCIENCE, INFORMATION SYSTEMS

IET Networks Pub Date : 2022-10-14 DOI:10.1109/IET-ICETA56553.2022.9971497

Yi-Ren Chen, Shih-Hsu Huang

引用次数: 1

Abstract

Hardware obfuscation is a useful technique for IP (intellectual property) protection. Several previous works have paid attention to the design of obfuscated FSM (finite state machine). Their common way is to insert an extra obfuscation mode to prevent the attackers from entering the normal mode. Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation. The proposed design flow includes two main steps: RTL coding (for the obfuscation mode) followed by FPGA synthesis. Experiments with a real circuit show that the FPGA implementation can work without any degradation on circuit speed.

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模糊有限状态机实现的设计流程

硬件混淆是IP(知识产权)保护的一种有用技术。以前的一些工作已经关注了模糊有限状态机的设计。他们常用的方法是插入一个额外的混淆模式，以防止攻击者进入正常模式。基于混淆模式的概念，本文研究了FPGA实现的设计流程。提出的设计流程包括两个主要步骤:RTL编码(用于混淆模式)，然后是FPGA合成。实际电路的实验表明，FPGA实现可以在不降低电路速度的情况下工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Networks COMPUTER SCIENCE, INFORMATION SYSTEMS-

CiteScore

5.00

自引率

0.00%

发文量

审稿时长

33 weeks

期刊介绍： IET Networks covers the fundamental developments and advancing methodologies to achieve higher performance, optimized and dependable future networks. IET Networks is particularly interested in new ideas and superior solutions to the known and arising technological development bottlenecks at all levels of networking such as topologies, protocols, routing, relaying and resource-allocation for more efficient and more reliable provision of network services. Topics include, but are not limited to: Network Architecture, Design and Planning, Network Protocol, Software, Analysis, Simulation and Experiment, Network Technologies, Applications and Services, Network Security, Operation and Management.

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