A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573474

Y. Frans, Mohamed Elzeftawi, H. Hedayati, J. Im, V. Kireev, Toan Pham, Jaewook Shin, P. Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang

引用次数: 33

Abstract

A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.

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采用16nm FinFET的32路时间交错SAR ADC的56Gb/s PAM4有线收发器

采用16nm FinFET实现了56Gb/s PAM4有线收发器测试芯片。CML变送器在输出节点包含一个辅助电流注入，以保持PAM4幅度线性。接收机由恒定直流增益的连续时间线性均衡器和一个28GSa/s的32路时间交错SAR ADC组成。该收发器在14GHz的背板通道上实现了1e-8误码率，损耗为25dB，功耗为550mW，不包括DSP。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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