Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing

Abstract

Parallel prefix adder is a type of adder design which emphasizes the parallelism on carry propagations, and can trade-off between the circuit size and the logical depth. This paper proposes a novel approach to the optimization of parallel prefix structure, which is based on Simulated Annealing (SA), a stochastic search of solution space, with respect to parallel prefix structures. A coding scheme named “prefix sequence” for representing the structure of parallel prefix adder and its application to SA-based search are main proposals of this paper. Finally, the advantage of our approach is demonstrated through design experiment.