VHDL implementation of UART with BIST capability

Abstract

Manufacturing processes are extremely complex, inducing manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built-In-Self-Test (BIST). A Universal Asynchronous Receive/Transmit (UART) with BIST capability has the objectives of testing the UART on chip itself and no external devices are required to perform the test. This paper focuses on the VHDL implementation of UART with embedded BIST capability using FPGA technology. The paper presents the architecture of UART with BILBO which tests the UART for its correctability. The whole design is synthesized and verified using Xilinx ISE Simulator and Modelsim Simulator.