Current flattening circuit for DPA countermeasure

Abstract

In cryptographic applications, power consumption variations seen off-chip are a rich source of information for intruders to obtain secret or keying materials from the system. Differential Power Analysis (DPA) technique uses statistical functions to analyze the power consumption and extracts the secret keys from the cipher systems. Consequently, this side-channel information needs to be masked to make it very difficult or practically impossible to perform power analysis on the secured system. In this work, we propose an on-chip DPA countermeasure solution that can be added to an existing cryptographic core at the final design stage with minimal impact. The circuit was implemented in 0.18µm process and the results from detailed layout level simulations are presented in this work. The circuit has been verified to work with typical, fast and slow process parameters.