A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Abstract

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.