Design and implementation of area and delay optimized carry tree adders using FPGA

Abstract

Adders play an important role in digital circuits. Logarithmic adders are efficient in delay reduction of carry generation/propagation in contrary to linear adders. It is found from simulations that even logarithmic adders suffer from delay, chip area over head and additional latches in the presence of ripple carry adders at the time of FPGA realization. The main motive of this work is to design and develop optimizeddelay free adders by introducing the proposed leaf adder module. In this work, we propose optimized Kogge-Stone and Spanning tree adders based on carry-tree architecture. Our designs are simulated using Verilog HDL and implemented on Xilinx Virtex-5 FPGA for real time verification. Performance metrics such as delay and chip area are evaluated using our numerical simulations. It is shown from results that our optimized Kogge-Stone and Spanning tree adders achieve 13.9% and 1.5 % reduction in delay: 24% and26.5% in LUT reduction; and 25.9% and 23.8% in slice reduction respectively, compared to existing tree adders.