A design of FIR filter using CSD with minimum number of registers

Abstract

This paper proposes an algorithm to be used for the VLSI design of a FIR filter using a canonical signed digit (CSD) representation with a minimum number of registers. The coefficients represented by CSD have a common digit pattern, so that they can reduce the number of adders to calculate same digit patterns. The proposed method takes advantage of this technique without using more registers than that of the transfer function.